Unlike a conventional programmable logic device (PLD), an in-system programmable logic device (ISPLD) can be reprogrammed in place, i.e. without removal from the system in which it is deployed. The method of reprogramming a programmable logic device in place is known as in-system programming (ISP). The standard pins utilized in in-system programming include a serial data input pin (SDI), a serial data output pin (SDO), a select mode pin (MODE) and a shift clock pin (SCLK). In-system programming is discussed in application Ser. No. 07/695,356, filed May 3, 1991 and assigned to Lattice Semiconductor Corporation, which will issue as U.S. Pat. No. 5,237,218 on Aug. 17, 1993. This application is herein incorporated by reference.
U.S. Pat. No. 5,237,218 allows an in-system programmable logic device to be implemented using only one dedicated in-system programming pin (ISP bar). The additional in-system programming pins (MODE, SCLK, SDI and SDO) are made available by multiplexing pins which are used as functional pins (such as input pins) when not in in-system programming mode. The in-system programming is controlled by an instruction-based state machine. An instruction set is provided to control the in-system programming activities.
In integrated circuit testing, a technique called "boundary scan" has been developed in recent years. 0n Feb. 15, 1990, the Institute of Electrical and Electronics Engineers (IEEE) approved standard 1149.1-1990. This standard defines a standard test logic architecture for implementing boundary scan functions which can be included in an integrated circuit for the purpose of testing the integrated circuit. The test architecture is defined to include a test access port (TAP) having connections for a test clock pin (TCK), a test mode select pin (TMS), a test data input pin (TDI) and a test data output pin (TDO). The test architecture also includes a TAP controller (boundary-scan state machine). The state diagram of the TAP controller is shown in FIG. 1. The value shown adjacent to each state transition in FIG. 1 represents the signal present at TMS at the time of a rising edge at TCK. Finally, the test architecture includes an instruction register and a group of test data registers. The test data registers include at least a bypass register and a boundary-scan register. A block diagram of the test logic is illustrated in FIG. 2. IEEE Standard 1149.1-1990 is herein incorporated by reference.
Previously, in order to provide both in-system programming and standard test logic architecture in an integrated circuit (IC), eight pins were required. An example of a pin out of such an IC is illustrated in FIG. 3. The MODE, SDO, SDI, and SCLK pins provide the in-system programming functions and the TMS, TDO, TDI, and TCK pins provide the boundary-scan testing functions. Because the pins of an integrated circuit package are considered a scarce resource, minimizing the number of pins is highly desirable. Therefore, it is desirable to reduce the number of pins required for in-system programming and boundary-scan testing.
In addition, in-system programming and boundary-scan testing utilize different state machines to control each function. By eliminating one of these state machines, the silicon area required for such an IC would be reduced. Therefore, it is desirable to utilize the same state machine to control both in-system programming and boundary-scan testing.